HY5117404C,hy5116404c 4mx4, extended data out mode this family is a 16m bit dynamic ram organized 4,194,304 x 4-bit configuration with extended data out mode cmos drams . extended data out mode is a kind of page mode which is useful for the read operation. the circuit and process design allow this device to achieve high performance and low power dissipation. optional features are access time(50, 60 or 70ns) and refresh cycle(2k ref. or 4k ref.) and power consumption (normal or low power with self refresh). hyundai ? s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. description features ? extended data out operation ? read-modify-write capability ? ttl compatible inputs and outputs ? /cas-before-/ras, /ras-only, hidden and self refresh capability ? max. active power dissipation speed 50 2 k refresh 798 mw 4 k refresh 605 mw ? fast access time and cycle time speed 50 60 trac 50 ns 60 ns tcac 13 ns 15 ns thpc 20 ns 25 ns ? refresh cycle part number HY5117404C hy5116404c refresh 2 k 4 k normal 32 ms sl-part 256 ms this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licences are implied rev. 10/sep.97 ordering information part name HY5117404Cj refresh 2 k power package 24/26 pin soj HY5117404Cslj 2 k sl-part 24/26 pin soj HY5117404Ct 2 k 24/26 pin tsop-ii HY5117404Cslt 2 k sl-part hy5116404cj 4 k hy5116404cslj 4 k sl-part 60 660 mw 495 mw hyundai semiconductor ? jedec standard pinout ? 24/26-pin plastic soj (300mil) 24/26-pin plastic tsop-ii (300mil) ? single power supply of 5v 10% ? early write or output enable controlled write 1 * sl : low power with self refresh 64 ms hy5116404ct 4 k hy5116404cslt 4 k sl-part 70 550 mw 440 mw 70 70 ns 18 ns 30 ns 24/26 pin tsop-ii 24/26 pin soj 24/26 pin soj 24/26 pin tsop-ii 24/26 pin tsop-ii .com .com .com 4 .com u datasheet
HY5117404C,hy5116404c functional block diagram 2 4 mx4,edo dram rev. 10/sep.97 we cas oe data input buffer dq0~3 data output buffer dq0~3 cas clock generator cloumn predecoder (11/10)* refresh controller row predecoder (11/12)* column decoder sense amp i/o gate memory array 4,194,304 x 4 row decoder ras clock generator x16 parallel test substrate bias generator v cc v ss address buffer ras dq0 *( a11) for 4k refresh part (2 k refresh / 4k refresh)* (11/10)* (11/12)* 4 4 4 4 a0 a1 *( a11) a10 a2 refresh counter a3 a4 a5 a6 a7 a8 a9 dq1 dq2 dq3 .com .com .com .com 4 .com u datasheet
pin configuration (marking side) pin description / ras / cas row address strobe column address strobe / we write enable / oe output enable a0~a11 address input (4k refresh product) a0~a10 address input (2k refresh product) dq0~dq3 data in/out vcc power (5v) vss ground nc no connection pin name parameter 3 4 mx4,edo dram rev. 10/sep.97 ( n.c)* : for 2k refresh product 24/26 pin plastic soj (300mil) 24/26 pin plastic tsop-ii (300mil) v cc dq0 dq1 we ras a0 a1 a2 a3 v cc 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 v ss dq3 oe a10 a9 a8 a7 a6 v ss cas dq2 *( n.c) a11 a5 a4 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 v ss dq3 oe a9 a8 a7 a6 v ss cas dq2 a5 a4 v cc dq0 dq1 we ras a0 a1 a2 a3 v cc a10 *( n.c) a11 HY5117404C,hy5116404c .com .com .com .com 4 .com u datasheet
absolute maximum rating symbol t a parameter ambient temperature rating 0 to 70 unit c t stg storage temperature -55 to 150 c v in, v out voltage on any pin relative to v ss -1.0 to 7.0 v v cc voltage on v cc relative to v ss -1.0 to 7.0 v i os short circuit output current 50 ma p d power dissipation 1 w t solder soldering temperature ? time 260 ? 10 c ? sec note : operation at or above absolute maximum ratings can adversely affect device reliability symbol i li parameter input leakage current (any input) unit m a min -10 max 10 test condition v ss v in v cc + 1.0 all other pins not under test = v ss dc operating characteristic i lo output leakage current (any input) m a -10 10 v ss v out v cc /ras & /cas at v ih v ol output low voltage v - 0.4 i ol = 4.2 ma v oh output high voltage v 2.4 - i oh = -5.0 ma 4 recommended dc operating conditions symbol v cc parameter power supply voltage unit v max 5.5 typ 5.0 min 4.5 v ih input high voltage v v cc+ 1.0 - 2.4 v il input low voltage v 0.8 - -1.0 note : all voltages are referenced to v ss . ( t a = 0 c to 70 c ) 4 mx4,edo dram rev. 10/sep.97 HY5117404C,hy5116404c .com .com .com .com 4 .com u datasheet
dc characteristics symbol i cc1 parameter operating current speed 50 60 70 unit ma ( t a = 0 c to 70 c , v cc = 5v 10% , v ss = 0v, unless otherwise noted.) note 2 k ref 145 120 100 4 k ref 110 90 80 test condition / ras, /cas cycling t rc = t rc (min.) max. current i cc2 ttl standby current ma 2 1 2 1 / ras, /cas 3 v ih other inputs 3 v ss i cc3 / ras-only refresh current 50 60 70 ma 145 120 100 110 90 80 / ras cycling,/cas = v ih t rc = t rc (min.) i cc4 edo mode current 50 60 70 ma 120 100 80 90 80 70 / cas cycling, /ras = v il t hpc = t hpc (min.) i cc5 cmos standby current sl-part ma m a 1 300 1 300 / ras = /cas 3 v cc - 0.2v i cc6 / cas-before-/ras refresh current 50 60 70 ma 145 120 100 110 90 80 / ras & /cas = 0.2v t rc = t rc (min.) i cc7 battery back-up current (sl-part) m a 300 t rc =125 s (2k ref), 62.5 s (4k ref) /cas = cbr cycling or 0.2v /oe & /we = v cc - 0.2v address = vcc -0.2v or 0.2v dq0~dq3 = vcc -0.2, 0.2v or open i cc8 self refresh current (sl-part) m a 300 300 / ras & /cas = 0.2v other pins are same as i cc7 1. i cc1 , i cc3 , i cc4 and i cc6 depend on output loading and cycle rates( t rc and t hpc ). 2. specified values are obtained with output unloaded. 3. i cc is specified as an average current. in i cc1 , i cc3 , i cc6 , address can be changed only once while /ras=v il . in i cc4 , address can be changed maximum once while /cas=v ih within one edo mode cycle time t hpc . 4. only /ras(max.) = 1 s is applied to refresh of battery backup but tras (max.) = 10 s is to applied to normal functional operation. 5. icc5(max.) = 300 a, icc7 and icc8 are applied to sl-part only. 5 sl-part tras 300ns tras 1 s 500 300 500 4 mx4,edo dram rev. 10/sep.97 HY5117404C,hy5116404c .com .com .com .com 4 .com u datasheet
t rc random read or write cycle time 84 ns symbol parameter min max min max unit note 50 ns 60 ns ac characteristics ( t a = 0 c to 70 c , v cc = 5 v 10% , v ss = 0v, unless otherwise noted.) read-modify-write cycle time 113 edo mode cycle time 20 edo mode read-modify-write cycle time 61 access time from /ras - access time from /cas - access time from column address - access time from column precharge - / cas to output low impedance output buffer turn-off delay from /cas transition time(rise and fall) / ras precharge time / ras pulse width / ras pulse width(edo mode) / ras hold time / cas hold time / cas pulse width / ras to /cas delay time / ras to column address delay time / cas to /ras precharge time / cas precharge time row address set-up time row address hold time column address set-up time column address hold time column address to /ras lead time read command set-up time read command hold time referenced to /cas t rwc t hpc t hprwc t rac t cac t aa t cpa t clz t cez t t t rp t ras t rasp t rsh t csh t cas t rcd t rad t crp t cp t asr t rah t asc t cah t ral t rcs t rch 3 3 2 30 50 50 13 40 8 18 10 5 8 0 8 0 10 25 0 0 - - - - 50 13 25 30 - 13 50 - 10 k 200 k - - 10 k 37 25 - - - - - - - - - 104 137 25 70 - - - - 3 3 2 40 60 60 15 45 11 20 15 5 10 0 10 0 10 30 0 0 - - - - 60 15 30 35 - 15 50 - 10 k 200 k - - 10 k 45 30 - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 2 2 5,6,7 5,6 5 5 5 8 3 6 7 11 9 read command hold time referenced to /ras t rrh 0 - 0 - ns 9 write command hold time write command pulse width t wch t wp 8 8 - - 10 10 - - ns ns write command to /ras lead time t rwl 10 - 12 - ns t cwl write command to /cas lead time ns 10 - 12 - min max 70 ns 124 160 30 78 - - - - 3 3 2 50 70 70 18 50 14 20 15 5 12 0 10 0 10 35 0 0 - - - - 70 18 35 40 - 18 50 - 10 k 200 k - - 10 k 52 35 - - - - - - - - - 0 - 10 10 - - 12 - 12 - 4 mx4,edo dram rev. 10/sep.97 HY5117404C,hy5116404c .com .com .com .com 4 .com u datasheet
symbol parameter min max min max unit note 50 ns 60 ns ac characteristics continued data-in set-up time data-in hold time refresh period(2048 cycles) refresh period(4096 cycles) refresh period(sl-part) write command set-up time / cas to /we delay time / ras to /we delay time column address to /we delay time / cas set-up time(cbr cycle) / cas hold time(cbr cycle) / ras to /cas precharge time / cas precharge time(cbr counter test) / ras hold time referenced to /oe / oe access time / oe to data delay time output buffer turn-off delay time from /oe / oe command hold time / we delay time from /cas precharge / ras hold time from /cas precharge / we to /ras precharge time(cbr cycle) / we to /ras hold time(cbr cycle) / ras pulse width(self refresh) t ds t dh t ref t wcs t cwd t rwd t awd t csr t chr t rpc t cpt t roh t oea t oed t oez t oeh t cpwd t rhcp t wrp t wrh t rass 0 - - - 0 30 67 42 5 10 5 15 10 - 13 3 13 47 30 10 10 100 k - - 32 64 256 - - - - - - - - - 13 - 13 - - - - - - 0 10 - - - 0 34 79 49 5 10 5 20 10 - 15 3 15 54 35 10 10 100 k - - 32 64 256 - - - - - - - - - 15 - 15 - - - - - - ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 10 10 11 11 11 11 8 11 output data hold time output buffer turn off delay time from /ras / we to data delay time / oe precharge time t rps t chs t doh t rez t wez t wed t oep 90 -50 5 3 3 13 5 - - - 13 13 - - 110 -50 5 3 3 15 5 - - - 15 15 - - ns ns ns ns ns ns ns t wpe t och t cho / ras precharge time (self refresh) / cas hold time (self refresh) output buffer turn off delay time from /we / we pulse width (edo cycle) / oe to /cas hold time 5 5 - - 5 5 - - ns ns / cas hold time to /oe 5 - 5 - ns min max 0 10 - - - 0 40 92 57 5 10 5 25 10 - 18 3 18 62 40 10 10 100 k - - 32 64 256 - - - - - - - - - 18 - 18 - - - - - - 130 -50 5 3 3 18 5 - - - 18 18 - - 5 5 - - 5 - 70 ns 4 mx4,edo dram rev. 10/sep.97 HY5117404C,hy5116404c .com .com .com .com 4 .com u datasheet
symbol parameter min max min max unit note 50 ns 60 ns test mode / cas to /we delay time / ras to /we delay time column address to /we delay time / oe access time / oe to data delay time / oe command hold time / we delay time from /cas precharge t cwd t rwd t awd t oea t oed t oeh t cpwd 35 72 47 - 18 18 52 - - - 18 - - - 39 84 54 - 20 20 59 - - - 20 - - - ns ns ns ns ns ns ns 11 11 11 11 min max 45 97 62 - 23 23 67 - - - 23 - - - 70 ns t rc random read or write cycle time 89 ns read-modify-write cycle time 118 edo mode cycle time 25 edo mode read-modify-write cycle time 66 access time from /ras - access time from /cas - access time from column address - access time from column precharge - t rwc t hpc t hprwc t rac t cac t aa t cpa - - - - 55 18 30 35 109 142 30 75 - - - - - - - - 65 20 35 40 ns ns ns ns ns ns ns 2 2 5,6,7 5,6 5,7 5 129 165 35 83 - - - - - - - - 75 23 40 45 / ras pulse width / ras pulse width(edo mode) / ras hold time / cas hold time / cas pulse width t ras t rasp t rsh t csh t cas 55 55 18 45 13 10 k 200 k - - 10 k 65 65 20 50 16 10 k 200 k - - 10 k ns ns ns ns ns 75 75 23 55 19 10 k 200 k - - 10 k column address to /ras lead time t ral 30 - 35 - ns 40 - in test mode, data are written into 16 sectors (each is composed of 1m bits) in parallel and retrieved the same way. column address a0 and a1 are not used. if, upon reading, 4-bit data from 4sectors connected to one dq pin are equal (all `1`s or `0`s), the dq pin indicates a `1`. if they are not equal, the dq indicates a `0`. the 4mx4 dram can be tested in the same way as a 1mx4 dram is tested. /we (when in /cas-before-/ras cycle) puts the 4mx4 dram into test mode and a /cas-before-/ras or a /ras-only refresh cycle put it back into normal mode. /we (when in /cas-before-/ras cycle) shall be used for the refresh operation in the test mode. the test mode function reduces test time(1/4 in case of n test pattern). 8 4 mx4,edo dram rev. 10/sep.97 HY5117404C,hy5116404c .com .com .com .com 4 .com u datasheet
note 1. an initial pause of 200 m s is required after power-up followed by 8 /ras only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cbr refresh cycles instead of 8 /ras-only refresh cycles are required. 2 t asc 3 t cp (min), assume t t =2ns. 3. vih(min.) and vil(max.) are reference levels for measuring timing of input signals. transition times are measured between vih(min.) and vil(max.) 4. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (ta=0 to 70 ?? c) is assured. 5. measured at voh=2.0v and vol=0.8v with a load equivalent to 2ttl loads and 100pf. 6. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 7. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 8. t wez , t rez , t cez and t oez define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 9. either t rch or t rrh must be satisfied for a read cycle. 10.these parameters are referenced to /cas leading edge in early write cycles and to /we leading edge in read-modify-write cycles. 11. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min) , and t cpwd 3 t cpwd (min.) , the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 12.if /ras goes to high before /cas high going,the open circuit condition of the output is achieved by /cas high going. if /cas goes to high before /ras high going,the open circuit condition of the output is achieved by /ras high going. 9 capacitance symbol c in1 parameter input capacitance (a0~a11) max 5 unit pf c in2 input capacitance (/ras, /cas, /we, /oe) 7 pf c dq data input / output capacitance (dq0~dq3) 7 pf ( t a = 25 c, v cc = 5v 10%, v ss = 0v and f=1mhz, unless otherwise noted.) typ . - - - 4 mx4,edo dram rev. 10/sep.97 HY5117404C,hy5116404c .com .com .com 4 .com u datasheet
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